Generally, when performing data transmission/reception through a transmission line with a large loss, and through a transmission line and a cable having a discontinuity in its characteristic impedance, an equalizing circuit (equalizer) for compensating for the degradation of a signal waveform due to the loss in the transmission line and the discontinuity characteristic impedance. The loss in the transmission line generates an ISI (inter-symbol interference) component in the reception waveform, and the discontinuity in the characteristic impedance generates a reflection component.
FIG. 1 is a conventional example of a data transmission/reception system through a backplane. While an output waveform from a transmitting circuit and an input waveform to a receiving circuit are illustrated, a distortion is generated in the input waveform to the receiving circuit due to an ISI component and a reflection component.
FIG. 2 is a configuration block diagram of a conventional example of a receiving circuit in a data transmission/reception system. In the drawing, transmission data transmitted from a transmitting circuit (Tx) 100 through a transmission line 101 is provided as input data RX_IN to a decision feedback equalizer (DFE) 105 in a receiving circuit (Rx) 102. The DFE 105 is an equalizing circuit corresponding to an IIR (infinite impulse response) filter as a typical equalizing circuit. Output RDT from the DFE 105 is converted from serial data to parallel data by a demultiplexer 106, and is output from the receiving circuit 102 as output data RX_OUT. The DFE 105 constitutes the IIR filter using output from a decision circuit that decides the logical value of an input signal, which is to be described in detail later.
A clock recovery unit 107 in the receiving circuit 102 in FIG. 2 detects temporal fluctuation in the output data, and outputs the result of the detection to a clock phase adjustment circuit 108 as a phase code. The clock phase adjustment circuit 108 adjusts the phase of a clock, and provides the DFE 105 with the adjusted clock for enabling the sampling at the middle position of the data in terms of time. A frequency dividing circuit 109 generates a clock required in the case of converting, for example, 10 GHz serial data into 330 MHz parallel data using the demultiplexer 106.
FIG. 3 is a configuration example of the decision feedback equalizer (DFE) 105 in FIG. 2. In the drawing, basically, the DFE is composed of a decision circuit 111 composed of a flip flop (FF); FF1121 to 112n−1 connected subsequently in series, their quantity being n−1; amplifiers 1141 to 114n that amplify the output of all FFs including the decision circuit 111; a subtractor 115 that subtracts the outputs of all amplifiers 1141 through 114n from the input data RX_IN input from the transmission line 101.
The operation of the DFE in FIG. 3 is described using FIG. 4 and FIG. 5. FIG. 4 is a diagram illustrating an example of a pulse response measurement system in a transmission line. In the drawing, a single pulse, i.e., a unit pulse is transmitted from the transmitting circuit 100 through the transmission line 101, and the response waveform is measured by a monitor 120 disposed in the receiving circuit 102. Here, the unit pulse output from the transmitting circuit 100 has a height corresponding to data “1”, and its width is one unit interval. The unit interval (UI) has a length corresponding to one cycle of a clock corresponding to the data transmission rate, and if the clock frequency is 5 GHz, one unit interval (UI) is 200 ps. In the following descriptions, the response at the input side in the receiving circuit 102 in the case of inputting the unit pulse described above to the transmission line 101 is referred to as “unit pulse response”, for simplification.
FIG. 5 is an example of the unit pulse response. The drawing illustrates the waveform of the unit pulse response in accordance with the time in units of unit intervals (UI), while assuming the input time of the unit pulse to the transmission line 101 to be time 0. The height a0 of the first peak is the original response component with respect to the input unit pulse; components a1 through a3 near the component a0 are the ISI components described above; and components an−1, an, an+1 . . . in distant positions from the peak a0 are the reflection components.
In FIG. 3, the decision circuit 111 decides the logical value of input signal data corresponding to the unit pulse response; outputs data H or L as the result; the data is shifted by one clock in each of the subsequent FF1121 through 112n−1; the outputs from all FFs are multiplied with amplification degrees a1 through an of the amplifiers 1141 through 114n; and the results of the multiplications are subtracted from the input data RX_IN by the subtractor 115. The amplification rates a1 through an are called tap coefficients and correspond to the values of the respective components in FIG. 5. In other words, the DFE 105 has amplitude values in accordance with an interference component as tap coefficients, and subtracts the interference component due to a previous input signal from the current input signal, of which further details are described in the following document.
N. Krishnapura et al. “A 5 Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission”, IEEE Int. Solid-State Circuits Conf., pp. 60-61, 585, February, 2005
Jan W. M. Bergmans, “DIGITAL BASEBAND TRANSMISSION AND RECORDING”, Kluwer Academic Publishers, Chap. 6, pp.265-300, 1996.
The IIR filter constituting the decision feedback equalizer as described above is conventionally disposed in the receiving circuit side. The IIR filter is effective for eliminating the ISI component caused by a loss in a transmission line and a cable, and for eliminating the reflection component due to a discontinuity in the characteristic impedance (mismatching in the termination resistance) at the input side of the receiving circuit. However, in a case such as when the point of discontinuity in the characteristic impedance exists along a transmission and a cable, the reflection component at the point of discontinuity is transmitted not only to the receiving circuit side but also to the transmitting circuit side. Although it is effective to eliminate, at the transmitting circuit side, the reflection component transmitted to the transmitting circuit side, there has been a problem that the reflection component may not be eliminated at the transmitting circuit side, since the transmitting circuit side is conventionally not equipped with an IIR filter.
In addition, there has been a general idea that it is more advantageous to dispose the IIR filter in the receiving circuit side. As described above, the receiving circuit converts, and outputs, input serial data into parallel data, while the flip flops constituting the demultiplexer for that purpose hold not only the current input data but also data for past several bits on the basis of the input data. Therefore, by composing the IIR filter using the output data from these flip flops, an equalizing circuit capable of suppressing the reflection component may be implemented while keeping the number of additional circuit elements to the minimum.
However, in response to the recent needs from users, a receiving circuit that is compatible with the configurations of the transmission line and cable in various forms may be required. For this reason, the development of an adaptive equalizing circuit that automatically determines the tap coefficients for the IIR filter is well underway. A control circuit to realize the algorithm for calculating the tap coefficients included in the adaptive equalizing circuit is generally large in size and there has been a problem that it is very difficult to include the control circuit for the adaptive equalization within the receiving circuit. By contrast, compared to the receiving circuit side, the transmitting circuit side is assumed to have some margins for circuit expansion to include the IIR filter.
In addition, at the receiving circuit side, there is a case of receiving data having a high bit error rate, and in this case, there is a possibility that the use of the IIR filter causes further degradation of the input signal waveform, because the tap coefficients are calculated on the basis of the wrong logic data. On the other hand, the logic data held at the transmitting circuit side is assumed to be always correct, and it is expected that by equipping the transmitting circuit side with the IIR filter, the calculation of the tap coefficient becomes accurate, and the reflection component is always suppressed accurately.